Pipelined Adc Design and Enhancement Techniques (Analog Circuits and Signal Processing) (Hardcover)

Pipelined Adc Design and Enhancement Techniques (Analog Circuits and Signal Processing) By Imran Ahmed Cover Image

Pipelined Adc Design and Enhancement Techniques (Analog Circuits and Signal Processing) (Hardcover)

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Chapter 1: Introduction. 1.1: Overview. 1.2: Chapter outline. SECTION I: PIPELINED ADC DESIGN. Chapter 2: ADC Architectures. 2.1: Overview. 2.2: Factors which determine ADC resolution and linearity. 2.3: ADC architectures. 2.4: ADC Figure-of-Merit. 2.5: Flash ADC. 2.6: SAR ADC. 2.7: Sub-sampling. 2.8: Summary. Chapter 3: Pipelined ADC Architecture Overview. 3.1: Overview. 3.2: Pipelined ADC introduction. 3.3: Multiplying Digital to Analog Converter (MDAC). 3.4: Opamp DC gain requirements. 3.5: Opamp bandwidth requirements. 3.6: Thermal noise requirements. 3.7: MDAC design - capacitor matching/linearity. 3.8: Error correction in Pipelined ADCs - relaxed sub-ADC requirements. 3.9: Sub-ADC design - comparator. 3.10: Front-end Sample-and-hold. 3.11: Summary. Chapter 4: Scaling Power with Sampling rate in an ADC. 4.1: Overview. 4.2: ADC power as a function of sampling rate. 4.3: Digital versus analog power. 4.4: Weak inversion model - EKV. 4.5: Weak inversion issues - mismatch. 4.6: Current scaling: Multiple design corners. 4.7: Current scaling - Bias point sensitivity. 4.8: Current scaling - IR drops. 4.9: Summary. Chapter 5: State of the art Pipelined ADC Design. 5.1: Overview. 5.2: Calibration in pipelined ADCs. 5.3: Power scalability with respect to sampling rate. 5.4: Power reduction techniques in Pipelined ADCs. 5.5: Summary. SECTION II: PIPELINED ADC ENHANCEMENT TECHNIQUES. Chapter 6: Rapid calibration of DAC and gain errors in a multi-bit pipeline stage. 6.1: Overview. 6.2: Motivation. 6.3: Rapid DAC + gain calibration architecture. 6.4: Circuit implementation. 6.5: Testing. 6.6: Measured results. 6.7: Summary. Chapter 7: A Power Scalable and Low Power Pipelined ADC. 7.1: Overview. 7.2: Power scalable architecture. 7.3: Current Modulated Power Scaling (CMPS). 7.4: Current switching issues. 7.5: Hybrid power scaling. 7.6: Detailedtrigger analysis. 7.7: Design of the digital state machine. 7.8: Rapid Power-On Opamps. 7.9: Common Mode Feed Back (CMFB) for Rapid Power-On Opamp. 7.10: Power reduction through current modulation. 7.11: Sample-and-Hold (S/H). 7.12: 1.5-bit MDAC. 7.13: Sub-ADC comparators. 7.14: Bias circuits. 7.15: Non overlapping clock generator. 7.16: Reference voltages. 7.17: Digital error correction. 7.18: Experimental implementation - PCB. 7.19: Experimental Implementation - Test setup. 7.20: Measured results. 7.21: Current scaled power. 7.22: Power scalable ADC - Power Scaling using CMPS. 7.23: Summary. Chapter 8: A sub-sampling ADC with embedded sample-and-hold. 8.1: Overview. 8.2: Motivation. 8.3: Embedded S/H technique. 8.4: Circuit implementation. 8.5: Test setup - PCB. 8.6: Test setup - Equipment. 8.7: Measured results. 8.8: Summary. Chapter 9: A capacitive charge pump based low power pipelined ADC. 9.1: Overview. 9.2: Motivation. 9.3: Architecture - capacitive charge pump based gain. 9.4: Effect of parasitic capacitors. 9.5: Unity gain buffer topology. 9.6: Noise analysis of capacitive charge pump based MDAC. 9.7: Calibration of pipeline stages. 9.8: Theoretical power savings. 9.9: Design specifications. 9.10: Circuit design. 9.11: Testing. 9.12: Measured results. 9.13: Summary. Chapter 10: Summary. 10.1: Summary. References. Index.
Product Details ISBN: 9789048186518
ISBN-10: 904818651X
Publisher: Springer
Publication Date: March 19th, 2010
Pages: 200
Language: English
Series: Analog Circuits and Signal Processing